During the past fifty years, the electronics and computing industries have been relentlessly propelled forward by ever decreasing sizes of basic electronic components, such as transistors and signal wires, and by correspondingly ever increasing component densities of integrated circuits, including processors and electronic memory chips. Eventually, however, it is expected that fundamental component-size limits will be reached in semiconductor-circuit-fabrication technologies based on photolithographic methods. As the size of components decreases below the resolution limit of ultraviolet light (i.e., a wavelength of about 193 nm), for example, far more technically demanding technologies need to be employed to create smaller components using photolithographic techniques, such as next generation lithography. Expensive semiconductor fabrication facilities may need to be rebuilt in order to use the new techniques. Many new obstacles are also expected to be encountered. For example, it is necessary to fabricate semiconductor devices through a series of photolithographic steps, with precise alignment of the masks used in each step with respect to the components already fabricated on the surface of a nascent semiconductor. As the component sizes decrease, precise alignment becomes more and more difficult and expensive. As another example, the probabilities that certain types of randomly distributed defects in semiconductor surfaces result in defective semiconductor devices may increase as the sizes of components manufactured on the semiconductor surfaces decrease, resulting in an increasing proportion of defective devices during manufacture, and a correspondingly lower yield of useful product. Ultimately, various quantum effects that arise only at molecular-scale distances may altogether overwhelm current approaches to component fabrication in semiconductors.
In view of these problems, researchers and developers have expended considerable research effort in fabricating submicroscale and nanoscale electronic devices using alternative technologies. Nanoscale electronic devices generally employ nanoscale signal wires having widths, and nanoscale components having dimensions, of less than 100 nanometers. More densely fabricated nanoscale electronic devices may employ nanoscale signal wires having widths, and nanoscale components having dimensions, of less than 50 nanometers, or, in certain types of devices, less than 10 nanometers.
Although general nanowire technologies have been developed, it is not necessarily straightforward to employ nanowire technologies to miniaturize existing types of circuits and structures. While it may be possible to tediously construct miniaturized, nanowire circuits similar to the much larger, current circuits, it is impractical, and often impossible, to manufacture such miniaturized circuits using current technologies. Even were such straightforwardly miniaturized circuits able to be feasibly manufactured, the much higher component densities that ensue from combining together nanoscale components necessitate much different strategies related to removing waste heat produced by the circuits. In addition, the electronic properties of substances may change dramatically at nanoscale dimensions, so that different types of approaches and substances may need to be employed for fabricating even relatively simple, well-known circuits and subsystems at nanoscale dimensions. Thus, new implementation strategies and techniques need to be employed to develop and manufacture useful circuits and structures at nanoscale dimensions using nanowires.
Nanowire technologies have been developed to fabricate nanoscale electronic devices, such as multiplexer/demultiplexers, by selectively fabricating simple electronic components, such as conductors, transistors, resistors, diodes, and other components, in the gaps between overlapping nanowires and address wires. However, during multiplexer/demultiplexer and logic array fabrication, a number of the electrical components may not be aligned with the nanowires. As a result, certain nanowires may not be addressable because connections cannot be established with overlapping address wires through electrical components. Designers, manufacturers, and users of these systems have recognized the need for multiplexer/demultiplexer and logic array designs that can tolerate electrical-component misalignment at nanowire and address-wire overlap points.